Gate Transfer Level Synthesis as an Automated Approach to Fine-Grain Pipelining

Register Transfer Level (RTL) synthesis method in clocked designs simplified circuit design and allowed design automation boosting VLSI progress for more than a decade. Shrinking technology and progressive increase in clock frequency is bringing clock to its crisis. Asynchronous circuits, which are believed to replace globally clocked designs in the future, remain out of the competition due to the design complexity of some automated approaches and poor results of other techniques. This work sketches the Gate Transfer Level (GTL) approach – it shows a general framework for automated synthesis of pipelined asynchronous circuits, presents certain aspects of GTL pipelines synthesis and informally demonstrates the equivalence of resulting GTL implementation to conventional RTL implementation of the same behavior. Experimental results show average 4.3x performance increase on MCNC benchmarks compared to synchronous RTL implementation.